Semiconductor memory device
US7468901B2 · kind B2 · utility
65Cited by
5References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2006 |
| Grant date | Dec 23, 2008 |
| Priority date | — |
| Expiry date | Aug 20, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4013
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a two-transistor gain cell structure, a semiconductor memory device capable of stable reading without malfunction and having small-area memory cells is provided. In a two-transistor gain cell memory having a write transistor and a read transistor, a write word line, a read word line, a write bit line, and a read bit line are separately provided, and voltages to be applied are independently set. Furthermore, a memory cell is connected to the same read word line and write bit line as those of an adjacent memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.