Process for fabrication of FinFETs

US7470570B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Jochen Beintner · Wappingers Falls, US
• Gary B. Bronner · Stormville, US
• Ramachandra Divakaruni · Ossining, US
• Yujun Li · Poughkeepsie, US

Key dates

• Filing date: Nov 14, 2006
• Grant date: Dec 30, 2008
• Expiry date: Mar 23, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/024

Abstract

A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.