System and method for controlling the formation of an interfacial oxide layer in a polysilicon emitter transistor
US7470594B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2005 |
| Grant date | Dec 30, 2008 |
| Priority date | — |
| Expiry date | May 28, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/905
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is disclosed for controlling the formation of an interfacial oxide layer in a polysilicon emitter transistor device. The interfacial oxide layer is formed between an underlying substrate of single crystal silicon and an upper layer of polysilicon. The current gain and the emitter resistance of the transistor device are related to the thickness of the interfacial oxide layer. The oxide of the interfacial oxide layer is grown in a low pressure, low temperature pure oxygen (O2) environment that greatly reduces the oxidation rate. The low oxidation rate allows the thickness of the interfacial oxide layer to be precisely controlled and sources of variation to be minimized in the manufacturing process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.