Patent · US Active

Dual damascene multi-level metallization

US7470613B2 · kind B2 · utility

5Cited by
7References
19Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJan 4, 2007
Grant dateDec 30, 2008
Priority date
Expiry dateJan 27, 2027

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/0002
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A method for forming an interconnect structure, the interconnect structure comprising: a lower level wire having a side and a bottom, the lower level wire comprising: a lower core conductor and a lower conductive liner, the lower conductive liner on the side and the bottom of the lower level wire; an upper level wire having a side and a bottom, the upper level wire comprising an upper core conductor and an upper conductive liner, the upper conductive liner on the side and the bottom of the upper level wire; and the upper conductive liner in contact with the lower core conductor and also in contact with the lower conductive liner in a liner-to-liner contact region.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.