Integrated assist features for epitaxial growth bulk/SOI hybrid tiles with compensation

US7470624B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Omar Zia · Austin, US
• Nigel G. Cave · Austin, US
• Venkat R. Kolagunta · Austin, US
• Ruiqi Tian · Pflugerville, US
• Edward O. Travis · Austin, US

Key dates

• Filing date: Jan 8, 2007
• Grant date: Dec 30, 2008
• Expiry date: Jan 18, 2027

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02P90/02
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and at least one epitaxial growth mask set (321, 331) from the first data set, wherein the at least one epitaxial growth mask set corresponds to tiles (305, 307) present on first (203) and second (207) distinct semiconductor surfaces; (c) reconfiguring the first trench CMP mask set to account for the at least one epitaxial growth mask set, thereby defining a second trench CMP mask set (308), wherein the second trench CMP mask set defines a set of trench CMP tiles; and (d) using the second trench CMP mask set to make a semiconductor device.