Structure of static random access memory with stress engineering for stability
US7471548B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 15, 2006 |
| Grant date | Dec 30, 2008 |
| Priority date | — |
| Expiry date | May 27, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
Abstract
An integrated circuit (IC) is provided that includes at least one static random access memory (SRAM) cell wherein performance of the SRAM cell is enhanced, yet with good stability and writability. In particular, the present invention provides an IC including at least one SRAM cell wherein the gamma ratio is about 1 or greater. The gamma ratio is increased with degraded pFET device performance. Morever, in the inventive IC there is no stress liner boundary present in the SRAM region and ion variation for all devices is reduced as compared to that of a conventional SRAM structure. The present invention provides an integrated circuit (IC) that comprises at least one SRAM cell including at least one nFET and at least one pFET; and a continuous relaxed stressed liner located above and adjoining the nFET and the pFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.