Method for fabricating a fan-in leadframe semiconductor package
US7473584B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 12, 2007 |
| Grant date | Jan 6, 2009 |
| Priority date | — |
| Expiry date | Aug 6, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package comprising a plurality of elongate leads which each have opposed inner and outer ends, opposed first and second surfaces, and a third surface which is disposed in opposed relation to the first surface and recessed relative to the second surface. The second surface of each lead is positioned in close proximity to the inner end thereof. The third surface of each lead extends to the outer end thereof. A semiconductor die is attached to portions of the first surfaces of at least some of the leads. The semiconductor die is itself electrically connected to at least some of the leads. A package body covers the semiconductor die and the leads such that the second surfaces of the leads are exposed in a bottom surface of the package body and the outer ends of the leads are exposed in respective side surfaces of the package body.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.