Double exposure double resist layer process for forming gate patterns
US7473648B2 · kind B2 · utility
4Cited by
1References
9Claims
0Family size
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Key dates
| Filing date | Mar 7, 2006 |
| Grant date | Jan 6, 2009 |
| Priority date | — |
| Expiry date | Jan 8, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a planar CMOS transistor divides the step of forming the gate layer into a first step of patterning a resist layer with a first portion of the gate layer pattern and then etching the polysilicon with the pattern of the gates. A second step patterns a second resist layer with the image of the gate pads and local interconnect and then etching the polysilicon with the pattern of the gate pads and local interconnect, thereby reducing the number of diffraction and other cross-talk from different exposed areas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.