Method for forming robust solder interconnect structures by reducing effects of seed layer underetching
US7473997B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2005 |
| Grant date | Jan 6, 2009 |
| Priority date | — |
| Expiry date | Apr 24, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P80/30
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.