High-speed interface circuit for semiconductor memory chips and memory system including the same

US7475187B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Peter Gregorius · Munich, DE
• Hermann Ruckerbauer · Radolfzell, DE
• Paul Wallner · Prien am Chiemsee, DE

Key dates

• Filing date: Sep 15, 2005
• Grant date: Jan 6, 2009
• Expiry date: Nov 15, 2026

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2207/107
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

In a semiconductor memory system, the memory chips are linked to a memory module in a shared loop forward architecture and connected in a point-to-point connection to a memory controller. Each memory chip includes a high-speed interface circuit including: a read and write data/command-and-address signal re-driver/transmitter path for re-driving serial read data and write data/command-and-address signals not destined for the semiconductor memory chip; and a main signal path which includes a serial-to-parallel converter and a synchronizer for serial-to-parallel converting and synchronizing with a reference clock signal write data/command-and-address signals destined for the semiconductor memory chip as well as a parallel-to-serial converter for parallel-to-serial converting read data signals read from a memory core of the memory chips, and a switch for inserting the parallel-to-serial converted read data signals into the re-driver/transmitter path. Optionally the high-speed interface circuit additionally includes a transparent re-driver/transmitter path not including any synchronizing circuitry.