Multi-threaded processor having compound instruction and operation formats
US7475222B2 · kind B2 · utility
13Cited by
3References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2005 |
| Grant date | Jan 6, 2009 |
| Priority date | — |
| Expiry date | Apr 1, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3853
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor comprises a memory, an instruction decoder coupled to the memory for decoding instructions retrieved therefrom, and a plurality of execution units for executing the decoded instructions. One or more of the instructions are in a compound instruction format in which a single instruction comprises multiple operation fields, with one or more of the operation fields each comprising at least an operation code field and a function field. The operation code field and the function field together specify a particular operation to be performed by one or more of the execution units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.