Method of manufacturing semiconductor device having dual gate electrode
US7476581B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 31, 2007 |
| Grant date | Jan 13, 2009 |
| Priority date | — |
| Expiry date | Oct 31, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0186
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Manufacturing of semiconductor device includes forming, at substrate main surface, PMOS and NMOS regions separated by PN film. Polysilicon is formed at surface. First insulating film serves as gate insulating film. Second insulating film is formed on polysilicon surface, in gate electrode region extending from PMOS to NMOS regions across PN film. Polysilicon layer is patterned with second insulating film, and first gate electrode extends from PMOS region surface to PN and second gate electrode extends from NMOS region to PN connecting to first gate electrode. At main surface, opposed first source and drain regions are formed by placing first gate electrode therebetween in plan view. At main surface, opposed second source and drain regions are formed by placing second gate electrode therebetween in plan view. The second insulating film, covering first and second gate electrodes is patterned and exposed on PN. Exposed first and second gate electrodes are silicidized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.