FET gate structure and fabrication process
US7476600B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 9, 2006 |
| Grant date | Jan 13, 2009 |
| Priority date | — |
| Expiry date | Sep 8, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6739
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention includes a method of fabricating a gate structure for a field effect transistor and the gate structure. The method includes providing a crystalline silicon substrate and epitaxially growing a gate insulating layer of crystalline rare earth insulating material on the crystalline silicon substrate. A gate stack of crystalline silicon is then epitaxially grown on the layer of crystalline rare earth insulating material and doped to provide a desired type of conductivity. The gate insulating layer and the gate stack are etched and a metal electrical contact is deposited on the epitaxially grown gate stack of crystalline silicon to define a gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.