Logic device having vertically extending metal-insulator-metal capacitor between interconnect layers and method of fabricating the same
US7476922B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2004 |
| Grant date | Jan 13, 2009 |
| Priority date | — |
| Expiry date | Feb 18, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76838
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A logic device having a vertically extending MIM capacitor between interconnect layers includes a semiconductor substrate. A lower interconnect layer is located over the semiconductor substrate, and an upper interconnect layer is located over the lower interconnect layer. A U-shaped lower metal plate is interposed between the lower interconnect layer and the upper interconnect layer. The U-shaped lower metal plate directly contacts the lower interconnect layer. The capacitor dielectric layer covers the inner surface of the lower metal plate. Further, the capacitor dielectric layer has an extension portion interposed between the brim of the lower metal plate and the upper interconnect layer. An upper metal plate covers the inner surface of the capacitor dielectric layer. The upper metal plate is in contact with the upper interconnect layer and is confined by the capacitor dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.