Flip chip package with advanced electrical and thermal properties for high current designs
US7476976B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2006 |
| Grant date | Jan 13, 2009 |
| Priority date | — |
| Expiry date | Dec 17, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A QFN package and method of making same is provided comprising a substrate having a metal line extending from a connection element on a perimeter region of the substrate to a high current contact pad on interior region of the substrate. A semiconductor chip having an active surface generally faces the interior region of the substrate, wherein a heat-dissipating patterned metal distribution layer is formed over the active surface and electrically connected to an active component thereon. A solder strip electrically and thermally connects the high current contact pad and the metal distribution layer, and a mold compound generally encapsulates the semiconductor chip. The solder strip is generally uniform in depth and surface area, wherein low electrical resistance and inductance is provided between the high current contact pad and the metal distribution layer. An integrated heat sink may be further formed or placed on a passive surface of the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.