Chip scale surface mounted device and process of manufacture
US7476979B2 · kind B2 · utility
3Cited by
49References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2006 |
| Grant date | Jan 13, 2009 |
| Priority date | — |
| Expiry date | Feb 6, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.