Patent · US Active

Structures and methods for heterogeneous low power programmable logic device

US7477073B1 · kind B1 · utility

17Cited by

8References

17Claims

0Family size

Assignee

XILINX, INC. · US

Inventors

Tim Tuan · San Jose, US
Arifur Rahman · San Jose, US
Satyaki Das · Palo Alto, US
Sean W. Kao · Campbell, US

Key dates

Filing date	Jun 16, 2006
Grant date	Jan 13, 2009
Priority date	—
Expiry date	Oct 28, 2026

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/17784
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A PLD utilizes a heterogeneous architecture to reduce power consumption of its active resources. The PLD's programmable resources are divided into a first partition and a second partition, where the resources of the first partition are optimized for low power consumption and the resources of the second partition are optimized for high performance. Portions of a user design containing non-critical timing paths are mapped to and implemented by the resources of the power-optimized first partition, and portions of the user design containing critical timing paths are mapped to and implemented by the resources of the performance-optimized second partition.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.