Systems for programmable chip enable and chip address in semiconductor memory
US7477545B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2007 |
| Grant date | Jan 13, 2009 |
| Priority date | — |
| Expiry date | Jul 22, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be re-addressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.