Merged MISR and output register without performance impact for circuits under test
US7478297B2 · kind B2 · utility
5Cited by
2References
4Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 22, 2007 |
| Grant date | Jan 13, 2009 |
| Priority date | — |
| Expiry date | Oct 22, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The output register of an array and the Multiple Input Signature Register (MISR) logic is implemented with one set of L1/L2 master/slave latches and single additional slave latch. This new combined logic uses less critical area on a chip without a performance impact on the array access time or circuit testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.