Timing driven logic block configuration
US7478356B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2005 |
| Grant date | Jan 13, 2009 |
| Priority date | — |
| Expiry date | Oct 11, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of configuring a logic block of a programmable logic device (PLD) during physical implementation of a circuit design, wherein ports of the logic block are selectively registered, can include identifying the logic block of the PLD, wherein the logic block is located on a critical path. For each of a plurality of selectively registerable portions of the logic block, the method can include computing input slacks and output slacks based upon potential register usage within the logic block. The method further can include determining register usage for the logic block by maximizing a function which depends upon a measure of worst case slack for pipeline stages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.