Methods of applying substrate bias to SOI CMOS circuits
US7479418B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2006 |
| Grant date | Jan 20, 2009 |
| Priority date | — |
| Expiry date | Jan 11, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6734
Abstract
The present invention relates to methods for reducing the threshold voltage difference between an n-type field effect transistor (n-FET) and a p-type field effect transistor (p-FET) in a complementary metal-oxide-semiconductor (CMOS) circuit located on a silicon-on-insulator (SOI) substrate. Specifically, a substrate bias voltage is applied to the CMOS circuit for differentially adjusting the threshold voltages of the n-FET and the p-FET. For example, a positive substrate bias voltage can be used to reduce the threshold voltage of the n-FET but increase that of the p-FET, while a negative substrate bias voltage can be used to increase the threshold voltage of the n-FET but reduce that of the p-FET. Further, two or more substrate bias voltages of different magnitudes and/or directions can be used for differentially adjusting the n-FET and p-FET threshold voltages in two or more different CMOS circuits or groups of CMOS circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.