Chip packaging process
US7482204B2 · kind B2 · utility
3Cited by
2References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2007 |
| Grant date | Jan 27, 2009 |
| Priority date | — |
| Expiry date | Dec 21, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip packaging process is provided. First, a cavity is formed on a heat sink. A first encapsulant is formed on the bottom of the cavity. A circuit substrate is disposed over the heat sink. The circuit substrate has an opening that corresponds in position to the cavity. Thereafter, a chip is disposed on the first encapsulant and the chip is electrically connected to the circuit substrate. Finally, a compound is deposited over the first encapsulant and the chip to form a chip package. The chip package is warp resistant and the chip packaging process increases overall production yield.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.