Self-aligned dual segment liner and method of manufacturing the same
US7482215B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 30, 2006 |
| Grant date | Jan 27, 2009 |
| Priority date | — |
| Expiry date | Mar 14, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a dual segment liner covering a first and a second set of semiconductor devices is provided. The method includes forming a first liner and a first protective layer on top thereof, the first liner covering the first set of semiconductor devices; forming a second liner, the second liner having a first section covering the first protective layer, a transitional section, and a second section covering the second set of semiconductor devices, the second section being self-aligned to the first liner via the transitional section; forming a second protective layer on top of the second section of the second liner; removing the first section and at least part of the transitional section of the second liner; and obtaining the dual segment liner including the first liner, the transitional section and the second section of the second liner. A semiconductor structure with a self-aligned dual segment liner formed in accordance with one embodiment of the invention is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.