Multi-thickness dielectric for semiconductor memory

US7482223B2 · kind B2 · utility

Assignee

• Sandisk, Inc. · US

Inventors

• Masaaki Higashitani · Cupertino, US
• Tuan Pham · Santa Clara, US

Key dates

• Filing date: Dec 22, 2004
• Grant date: Jan 27, 2009
• Expiry date: Dec 22, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

A process provides a gate dielectric layer of a first thickness for a memory array and for certain peripheral circuits on the same substrate as the memory array. High-voltage peripheral circuits are provided with a gate dielectric layer of a second thickness. Low-voltage peripheral circuits are provided with a gate dielectric layer of a third thickness. The process provides protection from subsequent process steps for a gate dielectric layer. Shallow trench isolation allows the memory array cells to be extremely small, thus providing high storage density.