Stress profile modulation in STI gap fill

US7482245B1 · kind B1 · utility

Assignee

• Novellus Systems, Inc. · US

Inventors

• Jengyi Yu · San Ramon, US
• Chi-I Lang · Cupertino, US
• Judy H. Huang · Los Gatos, US

Key dates

• Filing date: Jun 20, 2006
• Grant date: Jan 27, 2009
• Expiry date: Apr 12, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/60

Abstract

High density plasma (HDP) techniques form silicon oxide films having sequentially modulated stress profiles. The HDP techniques use low enough temperatures to deposit silicon oxide films in transistor architectures and fabrication processes effective for generating channel strain without adversely impacting transistor integrity. Methods involve partially filling a trench on a substrate with a portion of deposited dielectric using a high density plasma chemical vapor deposition process. The conditions of the process are configured to produce a first stress condition in the first portion of the deposited dielectric. The deposition process condition may then be modified to produce a different stress condition in deposited dielectric. The partially-filled trench may be further filled using the modified deposition process to produce additional dielectric and can be repeated until the trench is filled. Transistor strain can be generated in NMOS or PMOS devices using stress profile modulation in STI gap fill.