Etch before grind for semiconductor die singulation

US7482251B1 · kind B1 · utility

Assignee

• Impinj, Inc. · US

Inventors

• Ronald E. Paulsen · Woodinville, US
• Ronald L. Koepp · Seattle, US
• Yanjun Ma · Bellevue, US
• Larry Morrell · Kirkland, US
• Andrew E. Horch · Sunnyvale, US

Key dates

• Filing date: Aug 9, 2007
• Grant date: Jan 27, 2009
• Expiry date: Aug 9, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/78
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Methods are provided, and devices made by such methods. One of the methods includes procuring a semiconductor wafer, processing the wafer to form a plurality of circuits on a top side, forming trenches on the top side between the adjacent circuits, forming a trench passivation layer on side walls of the trenches, forming conductive bumps on the top side of the wafer; and removing material from the bottom side to thin the wafer, and eventually separate the wafer along the trenches into dies, where each die includes only one of the circuits.