Dual epitaxial layer for high voltage vertical conduction power MOSFET devices
US7482285B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2002 |
| Grant date | Jan 27, 2009 |
| Priority date | — |
| Expiry date | Oct 17, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/157
Abstract
The epitaxial silicon junction receiving layer of a power semiconductor device is formed of upper and lower layers. The lower layer has a resistivity of more than that of the upper layer and a thickness of more than that of the upper layer. The total thickness of the two layers is less than that of a single epitaxial layer that would be used for the same blocking voltage. P-N junctions are formed in the upper layer to define a vertical conduction power MOSFET device. The on-resistance is reduced more than 10% without any blocking voltage reduce. The upper epitaxial layer can be either by direct second layer deposition or by ion implantation of a uniform epitaxial layer followed by a driving process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.