Integrated semiconductor memory and method for electrically stressing an integrated semiconductor memory

US7482644B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Georg Eggers · Birkenfeld, DE
• Stephan Schröder · Birkenfeld, DE
• Manfred Proll · Dorfen, DE
• Herbert Benzinger · Birkenfeld, DE

Key dates

• Filing date: Feb 18, 2005
• Grant date: Jan 27, 2009
• Expiry date: Oct 16, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/488
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Semiconductor memories (1) have segmented word lines (5a, 5b), which in each case have a main word line (10a, 10b) made of a conductive metal and a plurality of interconnect segments (15a, 15b) coupled to the main word line (10a, 10b), which are coupled to the respective main word line (10a, 10b) in each case via at least one contact hole filling (11). If one of the contact hole fillings (11) is defective or at high resistance then functional errors of the semiconductor memory occur. The interconnect segments (15a, 15b) of two respective word lines (5a, 5b) can be short-circuited in pairs with the aid of switching units (20), whereby a static current (I) that flows via the contact hole fillings (11) can be used for electrically stressing the contact hole fillings (11). Electrical stressing of contact hole fillings of segmented word lines is thus made possible.