Probing pads in kerf area for wafer testing
US7482675B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2005 |
| Grant date | Jan 27, 2009 |
| Priority date | — |
| Expiry date | Nov 24, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure and a method for forming the same. The structure includes (a) a substrate having a top substrate surface; (b) an integrated circuit on the top substrate surface, wherein the integrated circuit includes a bond pad electrically connected to a transistor of the integrated circuit; (c) a protection ring on the top substrate surface and on a perimeter of the integrated circuit; (c) a kerf region on the top substrate surface, wherein the protection ring is sandwiched between and physically isolates the integrated circuit and the kerf region, wherein the kerf region includes a probe pad electrically connected to the bond pad, and wherein the kerf region is adapted to be destroyed by chip dicing without damaging the integrated circuit and the protection ring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.