Buffer insertion to reduce wirelength in VLSI circuits
US7484199B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2006 |
| Grant date | Jan 27, 2009 |
| Priority date | — |
| Expiry date | Aug 2, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Wirelength in a net of an integrated circuit design is reduced by forming clusters of sinks to be interconnected, inserting a buffer at each cluster, and providing branch connections between clusters by connecting a sink of one cluster to a buffer of another cluster, to create a buffer tree spanning all sinks. The buffers are inserted at a point on a respective bounding box of a cluster that is closest to a source for the net. A sink that provides a branch connection to the buffer of another cluster is the closest sink to that buffer (except for those sinks in the cluster). Clusters may be formed by examining different pairs of the sinks with different bounding boxes, and identifying one of the pairs whose bounding box has a lowest half-perimeter as the best pair for clustering.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.