Self-aligned dual stressed layers for NFET and PFET

US7485521B2 · kind B2 · utility

Assignees

• International Business Machines Corporation · US
• Advanced Micro Devices, Inc. · US

Inventors

• Huilong Zhu · Poughkeepsie, US
• Brian L. Tessier · Poughkeepsie, US
• Huicai Zhong · San Jose, US

Key dates

• Filing date: Jul 5, 2005
• Grant date: Feb 3, 2009
• Expiry date: Nov 7, 2026

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/938

Abstract

Methods are disclosed for forming self-aligned dual stressed layers for enhancing the performance of NFETs and PFETs. In one embodiment, a sacrificial layer is used to remove a previously deposited stressed layer. A mask position used to pattern the sacrificial layer is adjusted such that removal of the latter deposited stressed layer, using the sacrificial layer, leaves the dual stress layers in an aligned form. The methods result in dual stressed layers that do not overlap or underlap, thus avoiding processing problems created by those issues. A semiconductor device including the aligned dual stressed layers is also disclosed.