MOSFETs comprising source/drain regions with slanted upper surfaces, and method for fabricating the same
US7485524B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 21, 2006 |
| Grant date | Feb 3, 2009 |
| Priority date | — |
| Expiry date | Jul 28, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
Abstract
The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices comprising source and drain (S/D) regions having slanted upper surfaces with respect to a substrate surface. Such S/D regions may comprise semiconductor structures that are epitaxially grown in surface recesses in a semiconductor substrate. The surface recesses preferable each has a bottom surface that is parallel to the substrate surface, which is oriented along one of a first set of equivalent crystal planes, and one or more sidewall surfaces that are oriented along a second, different set of equivalent crystal planes. The slanted upper surfaces of the S/D regions function to improve the stress profile in the channel region as well as to reduce contact resistance of the MOSFET. Such S/D regions with slanted upper surfaces can be readily formed by crystallographic etching of the semiconductor substrate, followed by epitaxial growth of a semiconductor material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.