Inventor · Singapore, SG

Zhao Lun

21Patents
4h-index
56Co-inventors
62Inventor score

Filing activity: Jul 29, 2003 → Nov 4, 2015

Most-cited inventions

PatentTitleAreaCited byStatus
US9337306B2 Multi-phase source/drain/gate spacer-epi formation Electricity 26 Active
US9419101B1 Multi-layer spacer used in finFET Electricity 12 Active
US7485524B2 MOSFETs comprising source/drain regions with slanted upper surfaces, and method for fabricating the same Electricity 9 Active
US6998682B2 Method of forming a partially depleted silicon on insulator (PDSOI) transistor with a pad lock body extension Electricity 5 Expired
US7838390B2 Methods of forming integrated circuit devices having ion-cured electrically insulating layers therein Electricity 4 Active
US6905919B2 Method of forming a partially depleted silicon on insulator (PDSOI) transistor with a pad lock body extension Electricity 4 Expired
US8178417B2 Method of forming shallow trench isolation structures for integrated circuits Electricity 4 Active
US8716081B2 Capacitor top plate over source/drain to form a 1T memory device Electricity 4 Active
US8274115B2 Hybrid orientation substrate with stress layer Electricity 3 Active
US9362176B2 Uniform exposed raised structures for non-planar semiconductor devices Electricity 2 Active
US8053327B2 Method of manufacture of an integrated circuit system with self-aligned isolation structures Electricity 2 Active
US9059218B2 Reducing gate expansion after source and drain implant in gate last process Electricity 1 Active
US8987083B1 Uniform gate height for semiconductor structure with N and P type fins Electricity 1 Active
US7326609B2 Semiconductor device and fabrication method Electricity 0 Expired
US7795680B2 Integrated circuit system employing selective epitaxial growth technology Electricity 0 Active
US7259072B2 Shallow low energy ion implantation into pad oxide for improving threshold voltage stability Electricity 0 Expired
US7767577B2 Nested and isolated transistors with reduced impedance difference Electricity 0 Active
US8143651B2 Nested and isolated transistors with reduced impedance difference Electricity 0 Active
US9431528B2 Lithographic stack excluding SiARC and method of using same Electricity 0 Active
US7932178B2 Integrated circuit having a plurality of MOSFET devices Electricity 0 Active
US7999300B2 Memory cell structure and method for fabrication thereof Emerging Cross-Sectional Technologies 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.