Method of forming trench gate FETs with reduced gate to drain charge
US7485532B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2008 |
| Grant date | Feb 3, 2009 |
| Priority date | — |
| Expiry date | Mar 20, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/393
Abstract
A method for forming a FET includes the following steps. Trenches are formed in a semiconductor region of a first conductivity type. A well region of a second conductivity type is formed in the semiconductor region. Source regions of the first conductivity type are formed in the well region such that channel regions defined by a spacing between the source regions and a bottom surface of the well region are formed in the well region along opposing sidewalls of the trenches. A gate dielectric layer having a non-uniform thickness is formed along the opposing sidewalls of the trenches such that a variation in thickness of the gate dielectric layer along at least a lower portion of the channel regions is: (i) substantially linear, and (ii) inversely dependent on a variation in doping concentration in the lower portion of the channel regions. A gate electrode is formed in each trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.