Design structure for monitoring cross chip delay variation on a semiconductor device
US7487487B1 · kind B1 · utility
5Cited by
8References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2008 |
| Grant date | Feb 3, 2009 |
| Priority date | — |
| Expiry date | Apr 1, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A design structure for monitoring of the performance of semiconductor circuits, such as circuit delay, across a chip. The design structure may include a clock source and a plurality of process monitors. The design structure may be used to construct a “schmoo plot” by varying a frequency of the clock source to determine the delay of process monitors at various locations across the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.