Patent · US Active

Delay locked loop in synchronous semiconductor memory device and driving method thereof

US7489170B2 · kind B2 · utility

6Cited by
5References
14Claims
0Family size

Assignee

Inventors

Key dates

Filing dateSep 28, 2006
Grant dateFeb 10, 2009
Priority date—
Expiry dateSep 28, 2026

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03L7/0816
  • WIPO fieldBasic communication processes
  • WIPO sectorElectrical engineering

Abstract

A semiconductor memory device including a delay locked loop can minimize current consumption during a precharge power down mode. The delay locked loop includes a buffer control block for generating a clock buffer enable signal in response to first and second signals, wherein the first signal represents a precharge power down mode and the second signal represents a reset of the delay locked loop, a clock buffering block, controlled by the clock buffer enable signal, for buffering an external clock to generate a reference clock, and a feedback loop for delaying the reference clock until a delay locking state to thereby output a DLL output clock.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.