Method and semiconductor structure for monitoring the fabrication of interconnect structures and contacts in a semiconductor device
US7491555B2 · kind B2 · utility
8Cited by
3References
19Claims
0Family size
Assignee
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Key dates
| Filing date | May 23, 2006 |
| Grant date | Feb 17, 2009 |
| Priority date | — |
| Expiry date | Dec 27, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76843
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
By measuring an electric characteristic of a test pad that is connected to a plurality of test vias formed in accordance with a specified process flow for forming contacts and vias of a semiconductor device, one or more process specific parameters may quantitatively be estimated. Thus, a fast and precise measurement method for contacts and vias is provided in a non-destructive manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.