Inventor · Dresden, DE

Holger Schuehrer

16Patents
5h-index
19Co-inventors
59Inventor score

Filing activity: Apr 22, 2005 → Oct 16, 2019

Most-cited inventions

PatentTitleAreaCited byStatus
US7259091B2 Technique for forming a passivation layer prior to depositing a barrier layer in a copper metallization layer Electricity 258 Expired
US7396718B2 Technique for creating different mechanical strain in different channel regions by forming an etch stop layer stack having differently modified intrinsic stress Electricity 16 Active
US7491555B2 Method and semiconductor structure for monitoring the fabrication of interconnect structures and contacts in a semiconductor device Electricity 8 Active
US7410885B2 Method of reducing contamination by removing an interlayer dielectric from the substrate edge Electricity 7 Active
US8951907B2 Semiconductor devices having through-contacts and related fabrication methods Electricity 6 Active
US7781343B2 Semiconductor substrate having a protection layer at the substrate back side Electricity 5 Active
US8426312B2 Method of reducing contamination by providing an etch stop layer at the substrate edge Electricity 5 Active
US8384161B2 Contact optimization for enhancing stress transfer in closely spaced transistors Electricity 3 Active
US7638424B2 Technique for non-destructive metal delamination monitoring in semiconductor devices Electricity 2 Active
US8212346B2 Method and apparatus for reducing semiconductor package tensile stress Electricity 2 Active
US8129276B2 Void sealing in a dielectric material of a contact level of a semiconductor device comprising closely spaced transistors Electricity 2 Active
US8097536B2 Reducing metal voids in a metallization layer stack of a semiconductor device by providing a dielectric barrier layer Electricity 2 Active
US7820536B2 Method for removing a passivation layer prior to depositing a barrier layer in a copper metallization layer Electricity 1 Active
US8039400B2 Reducing contamination of semiconductor substrates during BEOL processing by performing a deposition/etch cycle during barrier deposition Emerging Cross-Sectional Technologies 1 Active
US7763476B2 Test structure for determining characteristics of semiconductor alloys in SOI transistors by x-ray diffraction Electricity 0 Active
US11127674B2 Back end of the line metal structure and method Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.