Undoped gate poly integration for improved gate patterning and cobalt silicide extendibility

US7491630B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Mehul D. Shroff · Austin, US
• Paul A. Grudowski · Austin, US
• Mark D. Hall · Austin, US
• Tab A. Stephens · Kyle, US

Key dates

• Filing date: Mar 15, 2006
• Grant date: Feb 17, 2009
• Expiry date: Jan 23, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch an intrinsic polysilicon layer (26) formed over a substrate (11), thereby forming etched gates (62, 64) having vertical sidewall profiles (61, 63). While a blanket nitrogen implant (46) of the intrinsic polysilicon layer (26) may occur prior to gate etch, more idealized vertical gate sidewall profiles (61, 63) are obtained by fully doping the gates (80, 100) during the source/drain implantation steps (71, 77, 91, 97) and after the gate etch.