Inventor · Kyle, TX, US

Tab A. Stephens

38Patents
10h-index
46Co-inventors
71Inventor score

Filing activity: Jul 28, 2003 → Apr 3, 2015

Most-cited inventions

PatentTitleAreaCited byStatus
US7504302B2 Process of forming a non-volatile memory cell including a capacitor structure Electricity 229 Active
US6919258B2 Semiconductor device incorporating a defect controlled strained channel structure and method of making the same Electricity 91 Expired
US7015517B2 Semiconductor device incorporating a defect controlled strained channel structure and method of making the same Electricity 80 Expired
US6831350B1 Semiconductor structure with different lattice constant materials and method for forming the same Electricity 78 Expired
US7339241B2 FinFET structure with contacts Electricity 41 Expired
US9094135B2 Die stack with optical TSVs Physics 16 Active
US6951783B2 Confined spacers for double gate transistor semiconductor fabrication process Electricity 15 Expired
US7091071B2 Semiconductor fabrication process including recessed source/drain regions in an SOI wafer Electricity 12 Expired
US9435952B2 Integration of a MEMS beam with optical waveguide and deflection in two dimensions Physics 12 Active
US7910482B2 Method of forming a finFET and structure Electricity 10 Active
US7491630B2 Undoped gate poly integration for improved gate patterning and cobalt silicide extendibility Electricity 7 Active
US9091820B2 Communication system die stack Physics 7 Active
US7829447B2 Semiconductor structure pattern formation Emerging Cross-Sectional Technologies 7 Active
US9810843B2 Optical backplane mirror Physics 6 Active
US9261556B2 Optical wafer and die probe testing Electricity 6 Active
US6972255B2 Semiconductor device having an organic anti-reflective coating (ARC) and method therefor Emerging Cross-Sectional Technologies 5 Expired
US7235471B2 Method for forming a semiconductor device having a silicide layer Electricity 5 Expired
US7659156B2 Method to selectively modulate gate work function through selective Ge condensation and high-K dielectric layer Electricity 4 Active
US7208424B2 Method of forming a semiconductor device having a metal layer Emerging Cross-Sectional Technologies 4 Expired
US8980734B2 Gate security feature Electricity 3 Active
US9070653B2 Microelectronic assembly having a heat spreader for a plurality of die Electricity 3 Active
US8680674B2 Methods and structures for reducing heat exposure of thermally sensitive semiconductor devices Electricity 3 Active
US8258035B2 Method to improve source/drain parasitics in vertical devices Electricity 3 Active
US7074713B2 Plasma enhanced nitride layer Electricity 3 Expired
US9318451B2 Wirebond recess for stacked die Electricity 2 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.