Manufacturing process for a transistor made of thin layers

US7491644B2 · kind B2 · utility

Assignees

• COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR
• STMicroelectronics SA

Inventors

• Maud Vinet · Voiron, FR
• Pascal Besson · Gap, FR
• Bernard Previtali · Grenoble, FR
• Christian Vizioz · Le Pont-de-Claix, FR

Key dates

• Filing date: Sep 9, 2005
• Grant date: Feb 17, 2009
• Expiry date: Feb 3, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0323

Abstract

A process for fabricating a transistor that includes a gate located in the immediate proximity of a dielectric includes a step of etching a layer of gate material. The gate etching step includes plasma etching of the gate layer over the major portion of its thickness so as to laterally define the gate and chemical etching of a residual portion of the gate layer so as to define the gate as far as the dielectric.