Method for fabricating group III nitride compound semiconductors and group III nitride compound semiconductor devices
US7491984B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2004 |
| Grant date | Feb 17, 2009 |
| Priority date | — |
| Expiry date | Sep 12, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02647
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a Group III nitride compound semiconductor with suppressed generation of threading dislocations.A GaN layer 31 is subjected to etching, so as to form an island-like structure having a shape of, for example, dot, stripe, or grid, thereby providing a trench/mesa structure, and a mask 4 is formed at the bottom of the trench such that the upper surface of the mask 4 is positioned below the top surface of the GaN layer 31. A GaN layer 32 is lateral-epitaxially grown with the top surface 31a of the mesa and sidewalls 31b of the trench serving as nuclei, to thereby bury the trench, and then epitaxial growth is effected in the vertical direction. In the upper region of the GaN layer 32 formed above the mask 4 through lateral epitaxial growth, propagation of threading dislocations contained in the GaN layer 31 can be prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.