Fully synchronous DLL with architected update window
US7492199B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2006 |
| Grant date | Feb 17, 2009 |
| Priority date | — |
| Expiry date | Jan 3, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/131
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention provides for a method for architecting a delay locked loop clock signal comprising: providing at least one clock signal to a clock signal splitter; alternately outputting the at least one clock signal from the clock signal splitter on at least two matched delay lines; alternately propagating the clock signal down each of the at least two matched delay lines; specifying a delay period for each of the matched delay lines with a control signal; updating said the two matched delay lines with the control signal when a fixed update window is always present on the matched delay lines; and distributing the clock signal to synchronously update the at least two matched delay lines, wherein no transitions are present in the fixed update window on the matched delay lines. Collect clock pulse outputs from the delay lines and reconstruct a delayed version of the input clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.