Memory with increased write margin bitcells
US7492627B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2006 |
| Grant date | Feb 17, 2009 |
| Priority date | — |
| Expiry date | Apr 26, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory comprising a first bit line, a second bit line, a word line, a first pair of cross-coupled inverters having a first input/output node and a second input/output node, a first power supply node and a second power supply node, wherein the first power supply node is coupled to a first power supply terminal, is provided. The memory further comprises a first gating transistor coupled between a second power supply terminal and the second power supply node, the first gating transistor receiving a first write enable signal that gates the gating transistor to a non-conductive condition during a write of the first pair of cross-coupled inverters. The memory further comprises a first pass transistor coupled to the first word line, the first input/output node, and the first bit line and a second pass transistor coupled to the first word line, the second input/output node, and the second bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.