Semiconductor memory device capable of effectively testing failure of data
US7492653B2 · kind B2 · utility
3Cited by
17References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2006 |
| Grant date | Feb 17, 2009 |
| Priority date | — |
| Expiry date | Apr 5, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1039
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to an apparatus and a method for detecting a failure of data in the semiconductor memory device. The semiconductor memory device according to the present invention includes: a global I/O line for transferring data between an external circuit and a local I/O line; an I/O sense amplifier for controlling a data transmission between the local I/O line and the global I/O line; and an I/O sense amplifier control unit for controlling the I/O sense amplifier in response to a test mode signal in order to test the semiconductor memory device, independent of the data outputted from a memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.