Stacking system and method

US7495334B2 · kind B2 · utility

Assignee

• Entorian Technologies, Inc · US

Inventors

• Russell Rapport · Austin, US
• James W. Cady · Austin, US
• James Wilder · Austin, US
• David Roper · Austin, US
• James Wehrly · Austin, US
• Jeff Buchle · Austin, US
• Julian Dowden · Austin, US

Key dates

• Filing date: Aug 4, 2005
• Grant date: Feb 24, 2009
• Expiry date: Dec 8, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H05K2201/10734
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a two-high CSP stack or module devised in accordance with a preferred embodiment of the present invention, two CSPs are stacked, with one CSP disposed above the other. The two CSPs are connected with flex circuitry. A form standard is disposed between the flex circuitry and a CSP in the stack. The form standard can take many configurations and may be used where flex circuits are used to connect CSPs to one another in stacked modules having two or more constituent CSPs. For example, in stacked modules that include four CSPs, three form standards are employed in preferred embodiments, although fewer may be used. The form standard provides a thermally conductive physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design.