Phase change memory fabricated using self-aligned processing
US7495946B2 · kind B2 · utility
20Cited by
9References
13Claims
0Family size
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Key dates
| Filing date | Mar 2, 2006 |
| Grant date | Feb 24, 2009 |
| Priority date | — |
| Expiry date | Mar 2, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/884
Abstract
A memory includes transistors in rows and columns providing an array and conductive lines in columns across the array. The memory includes phase change elements contacting the conductive lines and self-aligned to the conductive lines. Each phase change element is coupled to one side of a source-drain path of a transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.