Reverse bias trim operations in non-volatile memory
US7495947B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2006 |
| Grant date | Feb 24, 2009 |
| Priority date | — |
| Expiry date | Jul 31, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/165
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reverse bias trim operation for the reset state of a non-volatile memory system is disclosed. Non-volatile memory cells including a resistance change element undergo a reverse bias reset operation to change their resistance from a set state at a first level of resistance to a reset state at a second level of resistance. Certain memory cells in a set of cells that was reset may be deeply reset to a level of resistance beyond a target level for the reset state. A second reverse bias is applied to the set of memory cells to move the resistance of each cell that was deeply reset toward the target level of the reset state. A smaller reverse bias than used for the reset operation can shift the resistance of the cells back toward the set level and out of their deeply reset condition. The operation is self-limiting in that cells stop their resistance shifts upon reaching the target level. Cells that were not deeply reset are not affected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.