Method for partitioned erase and erase verification to compensate for capacitive coupling effects in non-volatile memory
US7495954B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 13, 2006 |
| Grant date | Feb 24, 2009 |
| Priority date | — |
| Expiry date | Apr 20, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3477
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A set of memory cells can be erased by individually erasing portions of the set in order to normalize the erase behavior of each memory cell and provide more consistent erase rates. An erase voltage pulse can be applied to the set of memory cells with a first group of cells biased for erase and a second group biased to inhibit erase. A second erase voltage pulse can then be applied with the second group biased for erase and the first group biased to inhibit erase. The groups are chosen so that the erase potentials for the cells in the first subset during the first pulse are about equal, so that the erase potentials for the cells in the second subset during the second pulse are about equal, and so that the erase potentials for the cells of the first subset are about the same as the erase potentials for the cells of the second subset. In one embodiment, the bias conditions for the string during each individual erase are selected so that every memory cell of the set will experience similar capacitive coupling effects from neighboring transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.