Fumitoshi Ito
39Patents
11h-index
36Co-inventors
71Inventor score
Filing activity: Oct 25, 2002 → Nov 3, 2017
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7499338B2 | Partitioned soft programming in non-volatile memory | Physics | 39 | Active |
| US7495954B2 | Method for partitioned erase and erase verification to compensate for capacitive coupling effects in non-volatile memory | Physics | 35 | Active |
| US7535766B2 | Systems for partitioned soft programming in non-volatile memory | Physics | 33 | Active |
| US9917093B2 | Inter-plane offset in backside contact via structures for a three-dimensional memory device | Electricity | 32 | Active |
| US7499317B2 | System for partitioned erase and erase verification in a non-volatile memory to compensate for capacitive coupling | Physics | 28 | Active |
| US7440326B2 | Programming non-volatile memory with improved boosting | Physics | 27 | Active |
| US7768826B2 | Methods for partitioned erase and erase verification in non-volatile memory to compensate for capacitive coupling effects | Physics | 25 | Active |
| US10103161B2 | Offset backside contact via structures for a three-dimensional memory device | Electricity | 23 | Active |
| US7087955B2 | Semiconductor device and a method of manufacturing the same | Electricity | 18 | Expired |
| US8885416B2 | Bit line current trip point modulation for reading nonvolatile storage elements | Physics | 12 | Active |
| US8400658B2 | Network device and workflow processing system | Physics | 11 | Active |
| US7730490B2 | System with user access-control information having signature and flow setting information for controlling order of performance of functions | Electricity | 10 | Active |
| US8026544B2 | Fabricating and operating a memory array having a multi-level cell region and a single-level cell region | Physics | 8 | Active |
| US8947699B2 | Image processing apparatus and control method thereof | Electricity | 6 | Active |
| US6734114B2 | Method for manufacturing semiconductor integrated circuit device | Electricity | 5 | Expired |
| US7349250B2 | Semiconductor device | Electricity | 5 | Expired |
| US7639836B2 | Image copying device and image processing system | Electricity | 5 | Active |
| US7705387B2 | Non-volatile memory with local boosting control implant | Physics | 4 | Active |
| US8988947B2 | Back bias during program verify of non-volatile storage | Physics | 4 | Active |
| US8942047B2 | Bit line current trip point modulation for reading nonvolatile storage elements | Physics | 3 | Active |
| US9148529B2 | Information processing apparatus, web server, control method and storage medium | Electricity | 3 | Active |
| US8354322B2 | Fabricating and operating a memory array having a multi-level cell region and a single-level cell region | Physics | 2 | Active |
| US10445477B2 | Information processing system, method of controlling the system, information processing apparatus, web server, and storage medium | Electricity | 2 | Active |
| US8699052B2 | Image forming apparatus, control method, and program | Electricity | 2 | Active |
| US8593665B2 | Image forming system and information processing apparatus | Electricity | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.